1 內(nèi)部連接器
1.1 主板連接器 (J9)
主板連接器是基于40柱連接器類型Atom Wafer 1.0mm雙排40pin或類似的
Note
Type
Signal
PIN
Signal
Type
Note
PWR
+3.3V
1
2
GND
PWR
PWR
+3.3V
3
4
NC
PWR
GND
5
6
NC
USB2_TH_DP
7
8
GND
PWR
USB2_TH_DP
9
10
NC
PWR
GND
11
12
NC
PWR
+5V
13
14
GND
PWR
DP_HPD
15
16
T1N
Complement Signal Link Lane 1
TOUCH_INT_EDP_N
17
18
T1P
True Signal Link Lane 1
TOUCH_RST_EDP_N
19
20
GND
PWR
I2C5_TCH_SCL_EDP
21
22
T0P
Complement Signal Lane 0
I2C5_TCH_SDA_EDP
23
24
T0N
True Signal Link Lane 0
PWR
GND
25
26
GND
PWR
PWR
+3.3V
27
28
AN_AUX_P
True Signal Auxiliary Channel
PWR
GND
29
30
AN_AUX_N
Comp Signal Auxiliary Channel
PWR
GND
31
32
GND
PWR
+VCC_EDP_BKLT
33
34
NC
+VCC_EDP_BKLT
35
36
NC
L_BKLT_CTRL
37
38
GND
PWR
L_BKLT_EN_R
39
40
GND
PWR
注意 ： 可用的線材裝備
1.2 LVDS 平板連接器 (J8)
Lvds連接器是基于40柱連接器類型Atom Wafer 1.0mm雙排40pin或類似的
Note
Type
Signal
PIN
Signal
Type
Note
PWR
+5V
1
2
LVDS_U3_P
LVDS
PWR
+3.3V
3
4
LVDS_U3_N
LVDS
BKL_EN
5
6
LVDS_U2_P
LVDS
BKL_PWM
7
8
LVDS_U2_N
LVDS
LVDS_DDC_CLK
9
10
LVDS_U1_P
LVDS
LVDS_DDC_DATA
11
12
LVDS_U1_N
LVDS
NC
13
14
LVDS_U0_P
LVDS
NC
15
16
LVDS_U0_N
LVDS
PWR
GND
17
18
LVD_UCLK_P
LVDS
LVDS_L3_P
19
20
LVD_UCLK_ N
LVDS
LVDS_L3_N
21
22
GND
PWR
LVDS
LVDS_L2_P
23
24
NC
LVDS
LVDS_L2_N
25
26
TOUCH_INT_EDP_N
LVDS
LVDS_L1_P
27
28
TOUCH_RST_EDP_N
LVDS
LVDS_L1_N
29
30
I2C5_TCH_SCL_EDP
LVDS
LVDS_L0_P
31
32
I2C5_TCH_SDA_EDP
LVDS
LVDS_L0_N
33
34
GND
PWR
LVD_LCLK_P
35
36
USB2_TH_DP
LVD_LCLK_ N
37
38
USB2_TH_DN
PWR
GND
39
40
GND
PWR
注意: 這個lvds接口支持單通道或者雙通道，spwg屏且*大支持1920x1080分辨率
Signal
Description
LVDS_L_TXn_P/N
LVDS 0 Channel data
LVDS_L_CLK_P/N
LVDS 0 Channel clock
LVDS_U_TXn_P/N
LVDS 1 Channel data
LVDS_U_CLK_P/N
LVDS 1 Channel clock
BKL_PWM
Backlight control (1), PWM signal to implement voltage in the range 0-3.3V
BKL_EN
Output Display Enable.
+5V
VCC supply to the display (1A Max.). Power sequencing depends on LVDS panel selection.
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